Up until now, a multi-layer wiring has been widely used in a printed board and a ceramic substrate on which a ceramic green sheet is laminated. In the multi-layer wiring, a technology for connecting upper and lower wirings to each other, which are separated by an interlayer insulation film through contact holes (also referred to as via-holes), is required. With the proliferation of high integration and high speed of LSI, high-density packages of a printed wiring substrate and a ceramic substrate have also been demanded. Recently, technologies for connecting upper and lower wirings to each other through fine contact holes have become important.
There are two methods for forming an interlayer insulation film. With one method, an insulation film is first formed on an entire substrate by a sputtering method, a vacuum evaporation method, or the like. Next, the insulation film is coated with a photoresist and subjected to pre-baking, exposure, and development to form resist patterns. Then, through-holes are formed in the insulation film by dry etching such as RIE. In this manner, the interlayer insulation film is formed. With the other method, a substrate is first coated with a photoresist and subjected to pre-baking, exposure, and development to form resist patterns. Next, an insulation film is formed by the sputtering method, the vacuum evaporation method, or the like and impregnated with an organic solvent. Thus, the insulation film on the patterned resist is lifted off to be removed together with the resist. In this manner, the interlayer insulation film is formed. Both methods require an expensive vacuum film forming apparatus and a large number of manufacturing steps and are poor in use efficiency of a material serving as the insulation film, which results in increased manufacturing costs.
On the other hand, the rear-surface circuit substrate of a flat panel display requires high definition, a high-speed response, and a low cost. In addition, there is demand for an active matrix driven electronic circuit that can be manufactured at lower cost. In the flat panel display, individual through-holes arranged at a constant pitch are formed; they have a circular or rectangular form having a size of about 30 μm through 60 μm at 200 dpi and have a circular or rectangular form having a size of about 80 μm through 120 μm at 100 dpi. As a method for manufacturing an interlayer insulation film having such individual through-holes at lower cost, attention has been paid to a printing technology, in particular, a screen printing method.
Furthermore, in manufacturing a flat panel display, an interlayer insulation film is formed on an active matrix driven electronic circuit and then individual electrodes and a metal wiring are further formed on the interlayer insulation film. At this time, the electronic circuit and the individual electrodes are electrically connected to each other by electrical wiring through the individual through-holes (via-holes) of the interlayer insulation film. The screen printing method is also effective for forming such an electrical wiring.
Generally, in the screen printing method, the viscosity of a paste, which is used for forming an insulation film having no pattern by solid printing and forming electrodes by soldering, is a hundred and several tens Pa·s. In forming the patterns of fine individual through-holes (via-holes) or the like, pattern defects such as oozing and feathering due to insufficient viscosity of the paste or insufficient thixotropy are likely to be caused. For this reason, it is difficult to form uniform and nondefective fine patterns in a printing region, and yields cannot be improved in mass production.
Patent Document 1 describes a method for improving a pattern resolution by providing a dummy pattern region outside the region of patterns subjected to positive printing (where emulsion patterns are transferred as they are). With this method, when a protection film is printed on a semiconductor wafer by the screen printing method, dummy patterns having a width of 50 through 100 μm are provided at an interval of 50 through 2000 μm outside chip patterns. When the chip patterns at a peripheral part are printed, a tacking force increases due to the dummy patterns. As a result, a sufficient bonding time for transferring a paste to the chip patterns can be obtained, thin spots are hardly generated at the edge of the protection film, and uniform printing patterns can be formed.
Patent Document 1: JP-A-2004-253575
However, the method described in Patent Document 1 causes an excessive tacking force due to wide dummy patterns. In forming the individual through-holes of a flat panel display, variations in pattern dimension due to the excessive tacking force may directly lead to an increased element area at the outermost peripheral part of the patterns and finally cause reduced image quality. Furthermore, defects such as feathering and oozing may be caused in the individual through-holes at the outermost peripheral part, which establishes the necessity for accurately controlling the shapes of the individual through-holes at the outermost peripheral part. Therefore, the patterns have to be arranged so that a transfer amount of the paste becomes uniform at the dummy pattern region, which results in difficulties in practice.